Converting Combinational Circuits into Pipelined Data Paths
نویسندگان
چکیده
This paper presents an algorithm which converts combinational circuits into pipelined datu paths under considerotion of U given clock priod. The approach minimizes the number of registers which is achieved by a recursive procedure selecting jor each pipeline level those circuit parts where U register location satisfies the timing constraints. The selection is based on an as-soon-as-possible and as-late-aspossible register location using a modified retiming ulgoriihm. Within these circuit parts a maximal jlow algoiithm guarantees to find the minimalnumber offlip-flopsfor a registef Because the algorithm runs in polynomial time and requires only a sparse graph representation of the circuit it is applicable to c/zSI circuits. It is integrated into a synthesis tool jor urithmetic building blocks and results are presented of its application to circuits ojsize up to 10,000 gates.
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